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0.25um |
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0.25 um 2.4/3.3V Process [CL250G/CM250G]
Shanghai Hua Hong NEC' s CL250G process is a foundry-compatible process for general purpose applications. CM250G process offers capacitors, high resistance poly resistors and native transistors for designs that require mixed-signal components.
CL250G & CM250G are now available to customers, with choice of libraries from multiple vendors. |
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| Process Features |
| Isolation |
STI |
| Well Formation |
Retrograded well |
| Gate Formation |
Ti silicide, Dual polarity poly |
| S/D Formation |
Ti salicide |
| ILD |
TEOS-NSG/CMP |
| Contact |
Ti/TiN/W-Plug |
| IMD |
TEOS-NSG/CMP |
| Via |
Ti/TiN/W-Plug |
| Metal |
AlCu/Ti/TiN |
| Passivation |
SiO2/SiN |
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| Device Performance |
| Parameter |
Unit |
Value |
| Vcc |
V |
2.5/3.3 |
| Tox (physical) |
A |
48/70 |
| Vt N/P |
V |
0.53/-0.53 |
| Idsat N/P |
uA/um |
600/-270 |
| Ioff N/P |
pA/um |
50/-50 |
| R.O. Delay |
pS/Stage |
38 |
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| Key Design Rule |
| Layer |
W/S |
| Diffusion |
0.30/0.36 |
| Poly |
0.24/0.36 |
| Contact |
0.30/0.30 |
| Metal 1 |
0.32/0.32 |
| Via 1-4 |
0.36/0.34 |
| Metal 2-4 |
0.40/0.40 |
| Metal 5 |
0.42/0.46 |
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0.25 um 2.5/3.3V Process with Embedded Flash [EF250G]
EF250G, which is a process based on CL250G, is Shanghai Hua Hong NEC' s embedded Flash solution. It is one of the most popular embedded non-volatile memory platforms in microprocessor, communications, consumer, and smart cards applications.
EF250G process is now available to customers, with a choice of libraries from multiple vendors.
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| Process Features |
| Isolation |
STI |
| Well Formation |
Twin Retrograded well |
| Gate Formation |
Ti silicide, Dual polarity poly |
| S/D Formation |
Ti salicide |
| ILD |
TEOS-NSG/CMP |
| Contact |
Ti/TiN/W-Plug |
| IMD |
TEOS-NSG/CMP |
| Via |
Ti/TiN/W-Plug |
| Metal |
AlCu/Ti/TiN |
| Passivation |
SiO2/SiN |
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| Device Performance |
| Parameter |
Unit |
Value |
| Vcc |
V |
2.5/3.3 |
| Tox (physical) |
A |
48/70/85/190 |
| Vt N/P |
V |
0.53/-0.53 |
| Idsat N/P |
uA/um |
600/-270 |
| Ioff N/P |
pA/um |
50/-50 |
| R.O. Delay |
pS/Stage |
38 |
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| Key Design Rule |
| Layer |
W/S |
| Diffusion |
0.30/0.36 |
| Poly |
0.24/0.36 |
| Contact |
0.30/0.30 |
| Metal 1 |
0.32/0.32 |
| Via 1-4 |
0.36/0.34 |
| Metal 2-4 |
0.40/0.40 |
| Metal 5 |
0.42/0.46 |
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0.25 um 2.5V/3.3V Process (UC2)
UC2 process offers competitive design rules for high-density communications products, high-end consumer products requiring low leakage and low power transistors. It is especially suitable for handheld devices such as PDA and IA.
UC2 process has been in volume production at Shanghai Hua Hong NEC since 2002. High-density standard cell libraries, production proven eSRAM and eROM compilers are available to Shanghai Hua Hong NEC' s customers. |
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| Process Features |
| Isolation |
Locos |
| Well Formation |
Retrograded well |
| Gate Formation |
Ti silicide, Dual polarity poly |
| S/D Formation |
Ti salicide |
| ILD |
TEOS-NSG/CMP |
| Contact |
Ti/TiN/W-Plug |
| IMD |
TEOS-NSG |
| Via |
Ti/TiN/W-Plug |
| Metal |
AlCu/Ti/TiN |
| Passivation |
SiO2/SiN |
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| Device Performance |
| Parameter |
Unit |
Value |
| Vcc |
V |
2.5/3.3 |
| Tox (physical) |
A |
58/85 |
| Vt N/P(Constant Current VT) |
V |
0.45/-0.45 |
| Idsat N/P |
uA/um |
432/-201 |
| Ioff N/P |
pA/um |
1/-2 |
| R.O. Delay |
pS/Stage |
36 |
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| Key Design Rule |
| Layer |
W/S |
| Diffusion |
0.56/0.36 |
| Poly |
0.24/0.36 |
| Contact |
0.36/0.44 |
| Metal 1 |
0.44/0.40 |
| Via 1 |
0.40/0.44 |
| Metal 2-3 |
0.44/0.40 |
| Via 2-3 |
0.40/0.44 |
| Metal 4 |
0.44/0.40 |
| Via 4 |
0.40/0.44 |
| Metal 5 |
1.68/1.68 (optional 0.68/0.52) |
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0.25 um 3.3V 4M RF Process (CA/CR25)
Shanghai Hua Hong NEC' s CA/CR25 process is an advanced 0.25 um mixed-signal analog CMOS platform that enables integration of less demanding RF circuit blocks with multi-million gate digital CMOS logic functions for wireless, multimedia and PC products applications. This process comes standard with 3.3 volt CMOS, vertical PNP, MIM capacitors, poly and N-well resistors, inductors, four layers of metal, a thick top-metal, and an optional varactor. |
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| Process Features |
| Isolation |
STI |
| Well Formation |
Retrograded well |
| Gate Formation |
Ti silicide, Dual polarity poly |
| S/D Formation |
Ti salicide |
| ILD |
TEOS-NSG/CMP |
| Contact |
Ti/TiN/W-Plug |
| IMD |
TEOS-NSG/CMP |
| Via |
Ti/TiN/W-Plug |
| Metal |
AlCu/Ti/TiN |
| Passivation |
SiO2/SiN |
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| Device Performance |
| Parameter |
Unit |
Value |
| Vcc |
V |
3.3 |
| Tox (physical) |
A |
70 |
| Vt N/P(Constant Current VT) |
V |
0.59/-0.74 |
| Idsat N/P |
uA/um |
550/-295 |
| Ioff N/P |
pA/um |
40/-40 |
| R.O. Delay |
pS/Stage |
45 |
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| Key Design Rule |
| Layer |
W/S |
| Diffusion |
0.32/0.38 |
| Poly |
0.36/0.36 |
| Contact |
0.32/0.28 |
| Metal 1 |
0.32/0.32 |
| Via 1-3 |
0.38/0.36 |
| Metal 2-3 |
0.44/0.40 |
| Via 2-3 |
0.40/0.40 |
| Metal 4 |
2.44/1.96 |
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